I. Field of the Invention
The present invention relates to the transfer of data within a system and more particularly to synchronous data transfer between users in a system having a shared data bus wherein address decoding is done in parallel with data transfer so that the transfer speed is enhanced.
II. Prior Art
In today's complex data communications equipment, many functions are linked together by various types of address and data bus structures. For example, as shown in FIG. 1, communications equipment 10 acts as an interface between a communications network 12 and a host 14. Communications equipment 10 comprises a number of modules, or users, each of which performs a different function. In this example, communications equipment 10 consists of a network interface module 16 and a host interface module 18 for interfacing with the communications network 12 and the host 14, respectively, a microprocessor 20 for providing control, two random access memories, RAM 1 22 and RAM 2 24, for storage, a clock generator 25 for generating system clock signals for the users, and a bus arbitrator/controller 26 for controlling the transfer of data within the communications equipment 10.
The users are interconnected within equipment 10 for data transfer by a data bus 28. The data bus 28 is normally a parallel bus structure of a predetermined number of bits in width. For instance, the data bus could be 18 bits wide, 16 bits being reserved for data and two bits being reserved for parity.
Control lines 30 extend between the users for conveying various messages therebetween. For example, each user vies, or bids, for use of the data bus 28 in order to send/receive information to/from a second user. For simplicity, in this document, the bidding user will be designated the "source" user and the second user will be designated the "destination" user although the data may be moving in either direction. Bus arbitrator/controller 26 determines which source user has the highest priority and sends a select signal (via control lines 30) to that source user allowing it exclusive access to the data bus for the next data transfer. In addition, bus arbitrator/controller 26 sends a R/W signal to the destination user indicating whether the transfer is to be a read or a write operation.
Destination user address lines 32 connected from the various source users to the bus arbitrator/controller are used to convey, from each source user, the address of the destination user with which it wishes to exchange information. The address of the corresponding destination user is conveyed by the bus arbitrator/controller to the selected destination user via selected destination user address bus 34.
One or more system clock signals are conveyed to the users from the clock generator (CLOCK GEN 25) via clock lines 33.
FIG. 2 illustrates a block diagram of circuitry which could be used in a bus arbitrator/controller 26 in a system having four users. Bus arbitrator/controller 26 consists of a multiplexer (MUX 36), a second multiplexer (MUX 38), and an arbitrator 40. MUX 36 receives destination user addresses via destination user address lines 32a, 32b, 32c, and 32d from each of the users in the system. Control lines 42 from arbitrator 40 indicate to MUX 36 which address should be selected. The selected address is output via selected destination user address bus 34.
MUX 38 receives the read/write (R/W) select lines 30a, 30b, 30c, and 30d from the users. These lines indicate whether the proposed operation by the source user will be a read or write operation with the destination user. Control lines 42 from arbitrator 40 indicate to MUX 38 which source user's R/W line is to be selected and the corresponding signal is output via control line 30e.
Arbitrator 40 receives bids for use of the data bus from the respective source users via source user bid lines 30f, 30g, 30h, and 30i. The arbitrator 40 determines which of the bidding users has the highest priority and selects the corresponding user via user select lines 30j, 30k, 30l, and 30m.
As discussed above, the data transfer amongst the users is synchronous, i.e., there is a continuous clock, or system clock, provided to each user and data is transferred in accordance with predetermined clock cycles. In many cases, the data transfer is accomplished by utilizing the system clock so that, during alternating clock cycles, the data bus is arbitrated or data is transferred between the users. In other words, during a first clock cycle, source users wishing to send or receive data over the data bus bid for exclusive use of the data bus and the bus arbitrator/controller determines which of the users bidding for use of the data bus has the highest priority. This is sometimes called the "arbitration cycle". During the next clock cycle, or the "data transfer cycle", the selected source user is notified via its user select line, the address of the destination user is sent over selected destination user address bus 34, and the data is transferred between the source and destination users. The following cycle is an arbitration cycle for the following data transfer cycle and so forth.
In some systems, time is saved by combining the data transfer of one cycle with the bus arbitration of the following cycle. In this manner, the total necessary time for arbitration/data transfer is reduced as the bus arbitration for the next data transfer cycle is being done in parallel with the present data transfer. An example of such a system is illustrated in the timing diagrams of FIG. 3.
In the example illustrated in FIG. 3, SYSTEM B CLOCK is providing the timing to the system, i.e., the rising edge of the SYSTEM B CLOCK represents the start of a new cycle. In the example, two users, Source User #1 and Source User #2, are each bidding for exclusive use of the data bus, Source User #1 having priority over Source User #2. As shown, both Source User #1 and Source User #2 Bid lines (corresponding to lines 30f and 30g of FIG. 2) go high during the first system clock cycle 50. Because Source User #1 has priority over Source User #2, the bus arbitrator/controller selects Source User #1 as indicated by the Source User #1 Select line (corresponding to line 30j, of FIG. 2). Destination user address 1 is multiplexed to the selected destination user address bus 34 by MUX 36 (FIG. 2).
During the following clock cycle 52, Source User #1 data is transferred, either sent or received by Source User #1, depending upon its R/W line. During that same clock cycle, Source User #2 is selected by bus arbitrator/controller as indicated by the Source User #2 Select line (corresponding to line 30k of FIG. 2). Data transfer for Source User #2 occurs during the next clock cycle 54 when the data is transmitted to/from the selected destination user at address destination user address 2.
As shown in the figure, Source User #1 again bids for access to the data bus during clock cycle 54 and is able to transmit/receive data during the following cycle 56. In this manner no clock cycles, except the initial clock cycle, are wasted by bus arbitration, i.e., data is being transferred during all clock cycles where there is data to be transferred.
There is a problem, however, which significantly slows the data transfer via the internal data bus of such systems. In many cases, after the selected destination user receives its address off the selected destination user address bus (34), address decoding must still be performed by the selected destination user prior to the data transfer. For instance, where the destination user comprises a group of registers, the address needs to be decoded into register selects. Also, some internal registers contain parity and others do not, i.e., a source user (register) having parity will send to a destination user (register) 16 bits of data plus two parity bits, while a source register having no parity will send just the 16 data bits. For those registers that do contain parity, parity is generated by the source register and checked by the destination register against existing parity. For those that do not contain parity, the parity checking mechanism has to be disabled. The destination user comprises the specific decode logic it requires to disable its parity checking mechanism.
Another example is where the destination user contains one or more RAMs and RAM selects must be generated from the address. For example, where a destination user contains a local store, a data buffer, a low instruction RAM, and a high instruction RAM, the following selects may be generated by decoding the selected destination user address: a local store select; a data buffer select; a low instruction RAM select; and a high instruction select. These RAM selects are generated by decode logic in the destination user.
In addition, the address must be verified that it is a valid address. For instance, an error code will be generated if the address indicates a write to a read-only address, a read to a write-only address or a write to protected storage.
The problem is that these and other address decodes consume time during the data transfer cycle which could otherwise be used for transferring data between users. Consequently, a longer data transfer cycle is required so that the various decodes may be performed and the data may be transferred.